SiMa.ai’s MLSoC Development Kit contains everything you need to evaluate, prototype and demonstrate your computer vision ML applications on the developer board using the contained MLSoC purpose-built silicon from SiMa.ai. The Development Kit combines a compact Developer Board based upon SiMa's HHHL PCIe production board that has been modified to expose interfaces utilized by developers and accommodates operation stand-alone on a lab bench environment as well as able to embed in a PCIe platform. This on-bench or in PC configuration options offer flexibility to support different developer profiles.
Out of the Box
Developers want to get the tools and hardware up and running quickly so they can evaluate and learn the new SiMa.ai edge ML platform. The Developer Kit provides an Out-of-Box set of all components that you need and a guide to make this a breeze and let developers focus on their evaluation.
Evaluate
The first step an ML developer will want to do is establish the ML model performance and accuracy on a target platform and assess the capabilities, time and effort in compiling models of interest. Palette™ provides quantization and compilation of a developer’s model using Palette’s compiler. Utilize Palette’s silicon software image build and deploy tools to program the developer board. The developer kit provides the ability to execute these builds and provide KPIs such as; frames per second (fps), latency, accuracy, % loading of compute resources and memory footprint. Palette, running in a Docker on a desktop, supports ARM cross compilation with libraries to generate code for the SoC, a platform build, test and deploy tool suite to create complete ML applications.
Prototype
The next step an ML developer will want to do is integrate this model into a potential application or use case, including ML model pre and post processing functions. To accelerate the prototyping phase, Palette adds the ability to quickly code, build and evaluate a pipeline using your own ML models. Developers can Python scripting using SiMa APIs for the functional pipeline, avoiding the complex embedded optimization often needed for on-device execution. These APIs bind your Python code to the device execution environment and will execute on device as a complete functioning pipeline. Pushbutton build and deploy loads this image into the Developer board for execution. This proof-of-concept application can validate the functionality of the pipeline as well as provide an early demonstration vehicle.
Demonstrate
Quickly bring a real-time data stream to the platform, execute a pipeline on this data stream and display the performance results in real-time running on the MLSoC silicon for use case demonstrations. GStreamer example pipelines included in the Palette software release can be run out of the box to demonstrate real-time streaming performance. Customer pipelines can leverage these pipeline designs that take advantage of GStreamer to get higher utilization of compute resources and higher fps. The developer board processes the pipelines and displays the metadata overlaid on the host PC. Add additional cameras to provide multi-camera processing capabilities.
MLSoC Developer Board:
The MLSoC Developer Board is based upon our PCIe half-height, half-length production board but is modified to operate on a lab bench environment with access to is a versatile board that uses the SiMa.ai Machine Learning System on Chip (MLSoC) device.
On Bench: PCIe edge connector covered in protective coating and a plate with four footings under the board, a micro-USB connector provides power for operation on a lab bench.
In PCs: The PCIe form factor (68.9mm x 160mm) using a standard 98-pin PCB edge connector to slot into any standard host PC or motherboard. A bracket is included to assist in securing to a PC.
Low Power Board: Typical workloads 10-15W. Supports PCIe Gen 4.0 up to x8 lanes, LPDDR4 x4, I2C x2, eMMC, uSD card, QSPI-8 x1, 1G Ethernet x2 ports via RJ45, UART x2, and GPIO interfaces.
Machine Learning Accelerator (MLA): providing up to 50 Tera Ops Per Second (50 TOPS) for neural network computation.
Application Processing Unit (APU): a cluster of four ARM Cortext-A65 dual threaded processors operating up to 1.15 GHz to deliver up to 15K Dhry stone MIPs, eliminates the need for an external CPU or PC host.
Video Encoder/Decoder: supports the H.264/H.265 compression standards with support for baseline/main/high profiles, 4:2:0 sub sampling with 8-bit precision. The encoder supports rates up to 4Kp30, while the decoder supports up to 4Kp60
Computer Vision Unit (CVU):
consists of a four core Synopsys ARC EV74 video processor supporting up to 600 16-bit GOPS
Incorporated for optimized execution of computer vision algorithms used in ML pre and post processing and other pipeline processing functions
Contained in Development Kit 2:
Developer Board (HHHL)
Type C Power adaptor & Type C to micro USB – cable
Ethernet Cable
UART Cable to USB
PCIe Mounting Bracket
Development Kit 2 Camera Bundle:
Development Kit 2 with Camera bundle to demonstrate GStreamer ML pipelines in real-time
RouteCAM_CU20 – Sony® IMX462 Full HD GigE Camera
Power-over-Ethernet camera with IEEE 802.3af compliance
Comes with PoE power adapter and cable
Houses Sony® Starvis IMX462 CMOS image sensor
Ultra-low light sensitivity & Superior near-infrared performance
High Dynamic Range (HDR)
On-board high-performance ISP
Supports 10Base-T, 100Base-TX and 1000base-T-modes
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{"id":9802335355197,"title":"SiMa.ai MLSoC DevKit 2.0","handle":"sima-ai-mlsoc-devkit","description":"\u003ch1 style=\"text-align: center;\" class=\"text-center lg:text-left text-white mb-4 lg:mb-8\"\u003e\u003cspan class=\"font-denim-medium text-[36px] md:leading-[40px] md:text-[64px] md:leading-[70px]\"\u003eElevate Your ML Journey\u003c\/span\u003e\u003c\/h1\u003e\n\u003cp\u003e\u003cmeta charset=\"UTF-8\"\u003e\u003cspan\u003eSiMa.ai’s MLSoC Development Kit contains everything you need to evaluate, prototype and demonstrate your computer vision ML applications on the developer board using the contained MLSoC purpose-built silicon from SiMa.ai. The Development Kit combines a compact Developer Board based upon SiMa's HHHL PCIe production board that has been modified to expose interfaces utilized by developers and accommodates operation stand-alone on a lab bench environment as well as able to embed in a PCIe platform. This on-bench or in PC configuration options offer flexibility to support different developer profiles.\u003c\/span\u003e\u003cspan\u003e\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2\u003e\u003cspan\u003e \u003c\/span\u003e\u003c\/h2\u003e\n\u003ch2\u003e\u003cspan\u003eOut of the Box\u003c\/span\u003e\u003c\/h2\u003e\n\u003cp\u003e\u003cspan\u003eDevelopers want to get the tools and hardware up and running quickly so they can evaluate and learn the new SiMa.ai edge ML platform. The Developer Kit provides an Out-of-Box set of all components that you need and a guide to make this a breeze and let developers focus on their evaluation.\u003c\/span\u003e\u003c\/p\u003e\n\u003cdiv style=\"text-align: center;\"\u003e\u003cimg src=\"https:\/\/sima.ai\/wp-content\/uploads\/2024\/12\/image-1-1.webp\" style=\"margin-bottom: 16px; float: none;\"\u003e\u003c\/div\u003e\n\u003ch2 style=\"text-align: left;\"\u003e \u003c\/h2\u003e\n\u003ch2 style=\"text-align: left;\"\u003eEvaluate\u003c\/h2\u003e\n\u003cp style=\"text-align: left;\"\u003e\u003cmeta charset=\"UTF-8\"\u003e\u003cspan\u003eThe first step an ML developer will want to do is establish the ML model performance and accuracy on a target platform and assess the capabilities, time and effort in compiling models of interest. Palette™ provides quantization and compilation of a developer’s model using Palette’s compiler. Utilize Palette’s silicon software image build and deploy tools to program the developer board. The developer kit provides the ability to execute these builds and provide KPIs such as; frames per second (fps), latency, accuracy, % loading of compute resources and memory footprint. Palette, running in a Docker on a desktop, supports ARM cross compilation with libraries to generate code for the SoC, a platform build, test and deploy tool suite to create complete ML applications.\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2 style=\"text-align: left;\"\u003e\u003cspan\u003e \u003c\/span\u003e\u003c\/h2\u003e\n\u003ch2 style=\"text-align: left;\"\u003e\u003cspan\u003ePrototype\u003c\/span\u003e\u003c\/h2\u003e\n\u003cp style=\"text-align: left;\"\u003e\u003cspan\u003eThe next step an ML developer will want to do is integrate this model into a potential application or use case, including ML model pre and post processing functions. To accelerate the prototyping phase, Palette adds the ability to quickly code, build and evaluate a pipeline using your own ML models. Developers can Python scripting using SiMa APIs for the functional pipeline, avoiding the complex embedded optimization often needed for on-device execution. These APIs bind your Python code to the device execution environment and will execute on device as a complete functioning pipeline. Pushbutton build and deploy loads this image into the Developer board for execution. This proof-of-concept application can validate the functionality of the pipeline as well as provide an early demonstration vehicle.\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2 style=\"text-align: left;\"\u003e\u003cspan\u003eDemonstrate\u003c\/span\u003e\u003c\/h2\u003e\n\u003cp\u003e\u003cspan\u003eQuickly bring a real-time data stream to the platform, execute a pipeline on this data stream and display the performance results in real-time running on the MLSoC silicon for use case demonstrations. GStreamer example pipelines included in the Palette software release can be run out of the box to demonstrate real-time streaming performance. Customer pipelines can leverage these pipeline designs that take advantage of GStreamer to get higher utilization of compute resources and higher fps. The developer board processes the pipelines and displays the metadata overlaid on the host PC. Add additional cameras to provide multi-camera processing capabilities.\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2\u003e \u003c\/h2\u003e\n\u003ch2\u003eMLSoC Developer Board:\u003c\/h2\u003e\n\u003cp\u003eThe MLSoC Developer Board is based upon our PCIe half-height, half-length production board but is modified to operate on a lab bench environment with access to is a versatile board that uses the SiMa.ai Machine Learning System on Chip (MLSoC) device.\u003c\/p\u003e\n\u003cul\u003e\n\u003cli\u003e\n\u003cstrong\u003eOn Bench:\u003c\/strong\u003e PCIe edge connector covered in protective coating and a plate with four footings under the board, a micro-USB connector provides power for operation on a lab bench.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eIn PCs:\u003c\/strong\u003e The PCIe form factor (68.9mm x 160mm) using a standard 98-pin PCB edge connector to slot into any standard host PC or motherboard. A bracket is included to assist in securing to a PC.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eLow Power Board: \u003c\/strong\u003eTypical workloads 10-15W. Supports PCIe Gen 4.0 up to x8 lanes, LPDDR4 x4, I2C x2, eMMC, uSD card, QSPI-8 x1, 1G Ethernet x2 ports via RJ45, UART x2, and GPIO interfaces.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eMachine Learning Accelerator (MLA):\u003c\/strong\u003e providing up to 50 Tera Ops Per Second (50 TOPS) for neural network computation.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eApplication Processing Unit (APU)\u003c\/strong\u003e: a cluster of four ARM Cortext-A65 dual threaded processors operating up to 1.15 GHz to deliver up to 15K Dhry stone MIPs, eliminates the need for an external CPU or PC host.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eVideo Encoder\/Decoder:\u003c\/strong\u003e supports the H.264\/H.265 compression standards with support for baseline\/main\/high profiles, 4:2:0 sub sampling with 8-bit precision. The encoder supports rates up to 4Kp30, while the decoder supports up to 4Kp60\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eComputer Vision Unit (CVU):\u003c\/strong\u003e\n\u003cul\u003e\n\u003cli\u003econsists of a four core Synopsys ARC EV74 video processor supporting up to 600 16-bit GOPS\u003c\/li\u003e\n\u003cli\u003eIncorporated for optimized execution of computer vision algorithms used in ML pre and post processing and other pipeline processing functions\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch2\u003e \u003c\/h2\u003e\n\u003ch2\u003eContained in Development Kit 2:\u003c\/h2\u003e\n\u003ctable style=\"width: 100%\" width=\"100%\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd style=\"border: 0px; text-align: center; vertical-align: top; width: 19.4495%;\"\u003e \u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0014\/4313\/5560\/files\/aGroup-272.svg?v=1737478186\" alt=\"\"\u003e\u003cbr\u003eDeveloper Board (HHHL)\u003c\/td\u003e\n\u003ctd style=\"border: 0px; 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The Development Kit combines a compact Developer Board based upon SiMa's HHHL PCIe production board that has been modified to expose interfaces utilized by developers and accommodates operation stand-alone on a lab bench environment as well as able to embed in a PCIe platform. This on-bench or in PC configuration options offer flexibility to support different developer profiles.\u003c\/span\u003e\u003cspan\u003e\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2\u003e\u003cspan\u003e \u003c\/span\u003e\u003c\/h2\u003e\n\u003ch2\u003e\u003cspan\u003eOut of the Box\u003c\/span\u003e\u003c\/h2\u003e\n\u003cp\u003e\u003cspan\u003eDevelopers want to get the tools and hardware up and running quickly so they can evaluate and learn the new SiMa.ai edge ML platform. The Developer Kit provides an Out-of-Box set of all components that you need and a guide to make this a breeze and let developers focus on their evaluation.\u003c\/span\u003e\u003c\/p\u003e\n\u003cdiv style=\"text-align: center;\"\u003e\u003cimg src=\"https:\/\/sima.ai\/wp-content\/uploads\/2024\/12\/image-1-1.webp\" style=\"margin-bottom: 16px; float: none;\"\u003e\u003c\/div\u003e\n\u003ch2 style=\"text-align: left;\"\u003e \u003c\/h2\u003e\n\u003ch2 style=\"text-align: left;\"\u003eEvaluate\u003c\/h2\u003e\n\u003cp style=\"text-align: left;\"\u003e\u003cmeta charset=\"UTF-8\"\u003e\u003cspan\u003eThe first step an ML developer will want to do is establish the ML model performance and accuracy on a target platform and assess the capabilities, time and effort in compiling models of interest. Palette™ provides quantization and compilation of a developer’s model using Palette’s compiler. Utilize Palette’s silicon software image build and deploy tools to program the developer board. The developer kit provides the ability to execute these builds and provide KPIs such as; frames per second (fps), latency, accuracy, % loading of compute resources and memory footprint. Palette, running in a Docker on a desktop, supports ARM cross compilation with libraries to generate code for the SoC, a platform build, test and deploy tool suite to create complete ML applications.\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2 style=\"text-align: left;\"\u003e\u003cspan\u003e \u003c\/span\u003e\u003c\/h2\u003e\n\u003ch2 style=\"text-align: left;\"\u003e\u003cspan\u003ePrototype\u003c\/span\u003e\u003c\/h2\u003e\n\u003cp style=\"text-align: left;\"\u003e\u003cspan\u003eThe next step an ML developer will want to do is integrate this model into a potential application or use case, including ML model pre and post processing functions. To accelerate the prototyping phase, Palette adds the ability to quickly code, build and evaluate a pipeline using your own ML models. Developers can Python scripting using SiMa APIs for the functional pipeline, avoiding the complex embedded optimization often needed for on-device execution. These APIs bind your Python code to the device execution environment and will execute on device as a complete functioning pipeline. Pushbutton build and deploy loads this image into the Developer board for execution. This proof-of-concept application can validate the functionality of the pipeline as well as provide an early demonstration vehicle.\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2 style=\"text-align: left;\"\u003e\u003cspan\u003eDemonstrate\u003c\/span\u003e\u003c\/h2\u003e\n\u003cp\u003e\u003cspan\u003eQuickly bring a real-time data stream to the platform, execute a pipeline on this data stream and display the performance results in real-time running on the MLSoC silicon for use case demonstrations. GStreamer example pipelines included in the Palette software release can be run out of the box to demonstrate real-time streaming performance. Customer pipelines can leverage these pipeline designs that take advantage of GStreamer to get higher utilization of compute resources and higher fps. The developer board processes the pipelines and displays the metadata overlaid on the host PC. Add additional cameras to provide multi-camera processing capabilities.\u003c\/span\u003e\u003c\/p\u003e\n\u003ch2\u003e \u003c\/h2\u003e\n\u003ch2\u003eMLSoC Developer Board:\u003c\/h2\u003e\n\u003cp\u003eThe MLSoC Developer Board is based upon our PCIe half-height, half-length production board but is modified to operate on a lab bench environment with access to is a versatile board that uses the SiMa.ai Machine Learning System on Chip (MLSoC) device.\u003c\/p\u003e\n\u003cul\u003e\n\u003cli\u003e\n\u003cstrong\u003eOn Bench:\u003c\/strong\u003e PCIe edge connector covered in protective coating and a plate with four footings under the board, a micro-USB connector provides power for operation on a lab bench.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eIn PCs:\u003c\/strong\u003e The PCIe form factor (68.9mm x 160mm) using a standard 98-pin PCB edge connector to slot into any standard host PC or motherboard. A bracket is included to assist in securing to a PC.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eLow Power Board: \u003c\/strong\u003eTypical workloads 10-15W. Supports PCIe Gen 4.0 up to x8 lanes, LPDDR4 x4, I2C x2, eMMC, uSD card, QSPI-8 x1, 1G Ethernet x2 ports via RJ45, UART x2, and GPIO interfaces.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eMachine Learning Accelerator (MLA):\u003c\/strong\u003e providing up to 50 Tera Ops Per Second (50 TOPS) for neural network computation.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eApplication Processing Unit (APU)\u003c\/strong\u003e: a cluster of four ARM Cortext-A65 dual threaded processors operating up to 1.15 GHz to deliver up to 15K Dhry stone MIPs, eliminates the need for an external CPU or PC host.\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eVideo Encoder\/Decoder:\u003c\/strong\u003e supports the H.264\/H.265 compression standards with support for baseline\/main\/high profiles, 4:2:0 sub sampling with 8-bit precision. The encoder supports rates up to 4Kp30, while the decoder supports up to 4Kp60\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eComputer Vision Unit (CVU):\u003c\/strong\u003e\n\u003cul\u003e\n\u003cli\u003econsists of a four core Synopsys ARC EV74 video processor supporting up to 600 16-bit GOPS\u003c\/li\u003e\n\u003cli\u003eIncorporated for optimized execution of computer vision algorithms used in ML pre and post processing and other pipeline processing functions\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch2\u003e \u003c\/h2\u003e\n\u003ch2\u003eContained in Development Kit 2:\u003c\/h2\u003e\n\u003ctable style=\"width: 100%\" width=\"100%\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd style=\"border: 0px; text-align: center; vertical-align: top; width: 19.4495%;\"\u003e \u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0014\/4313\/5560\/files\/aGroup-272.svg?v=1737478186\" alt=\"\"\u003e\u003cbr\u003eDeveloper Board (HHHL)\u003c\/td\u003e\n\u003ctd style=\"border: 0px; text-align: center; vertical-align: top; width: 31.7431%;\"\u003e\n\u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0014\/4313\/5560\/files\/aGroup-273.svg?v=1737478186\" alt=\"\"\u003e\u003cbr\u003eType C Power adaptor \u0026amp; Type C to micro USB – cable\u003c\/td\u003e\n\u003ctd style=\"border: 0px; text-align: center; vertical-align: top; width: 13.578%;\"\u003e\n\u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0014\/4313\/5560\/files\/Group-274.svg?v=1737478186\" alt=\"\"\u003e\u003cbr\u003eEthernet Cable\u003c\/td\u003e\n\u003ctd style=\"border: 0px; text-align: center; vertical-align: top; width: 15.7798%;\"\u003e\n\u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0014\/4313\/5560\/files\/Group-275.svg?v=1737478186\" alt=\"\"\u003e\u003cbr\u003eUART Cable to USB\u003c\/td\u003e\n\u003ctd style=\"border: 0px; text-align: center; vertical-align: top; width: 17.9817%;\"\u003e\n\u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0014\/4313\/5560\/files\/Group-276.svg?v=1737478186\" alt=\"\"\u003e\u003cbr\u003ePCIe Mounting Bracket\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003cp\u003e \u003c\/p\u003e\n\u003ch2\u003eDevelopment Kit 2 Camera Bundle:\u003c\/h2\u003e\n\u003cp\u003e\u003cspan style=\"color: rgb(128, 128, 128);\"\u003e\u003cstrong\u003eDevelopment Kit 2 with Camera bundle to demonstrate GStreamer ML pipelines in real-time\u003c\/strong\u003e\u003c\/span\u003e\u003c\/p\u003e\n\u003cul\u003e\n\u003cli\u003eRouteCAM_CU20 – Sony® IMX462 Full HD GigE Camera\u003c\/li\u003e\n\u003cli\u003ePower-over-Ethernet camera with IEEE 802.3af compliance\u003c\/li\u003e\n\u003cli\u003eComes with PoE power adapter and cable\u003c\/li\u003e\n\u003cli\u003eHouses Sony® Starvis IMX462 CMOS image sensor\u003c\/li\u003e\n\u003cli\u003eUltra-low light sensitivity \u0026amp; Superior near-infrared performance\u003c\/li\u003e\n\u003cli\u003eHigh Dynamic Range (HDR)\u003c\/li\u003e\n\u003cli\u003eOn-board high-performance ISP\u003c\/li\u003e\n\u003cli\u003eSupports 10Base-T, 100Base-TX and 1000base-T-modes\u003c\/li\u003e\n\u003cli\u003eDeveloper Kit Bundled with 1GB Ethernet Camera\u003c\/li\u003e\n\u003c\/ul\u003e"}
Despite showing available on the website and accepting my order, they called to tell me that the order was not available.
I had to then concede with another lower rated battery.
The issue doesn't end here.
I was supposed to get a refund for the difference in pricing, but despite reminders and calls (which were not answered), I didn't get any refund until I almost filed a police complaint against them.
